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also, how can i inspect such cases to make sure i understand the underlying decisions of yosys and nextpnr?
fpga verilog optimization lattice yosys share | improve this question edited yesterday hugo sereno ferreira asked days ago hugo sereno ferreira hugo sereno ferreira gold badge silver badges bronze badges \$\endgroup\$ add a comment | answers active oldest votes \$egingroup\$ as joshua says, something...
https://electronics.stackexchange.com/questions/473060/why-is-this-verilog-ram-modification-better-in-terms-of-resource-usage